A list of major past and ongoing projects I have been associated with.
A 12-bit Pipeline ADC is being designed in 40nm CMOS with a target sampling rate of 500MS/s, along with split ADC calibration technique to achieve lower calibration times. The ADC will be used to test the effectiveness of calibration algorithms, and hence needs to be highly power scalable.
Guide: Dr. Klaas Bult, Broadcom
An 8-bit Successive Approximation ADC is being designed for application in a cardiac sense amplifier. The ADC is being designed in IBM 130nm CMOS technology and is optimized for low speeds and ultra low power operation.
Guide: Prof. Wouter Serdijn, TU Delft
It involves the design of a WT-based analog signal processing frontend of a pacemaker. It consists of an ultra low power analog wavelet filter and low voltage A/D converter for detection of electrophysiological signals emanating from the heart, specifically detecting the QRS complex in the ECG.
Guide: Prof. Wouter Serdijn, TU Delft
This project aimed to implement the dynamic translinear principle using MOSFETs working in subthreshold region. Using DTL, we tried to design a low power Phase Locked Loop. The project ran into rough weather due to limitations of PSPICE in simulating complex non-linear systems like PLLs, and our own lack of expertise in this area at that time. But it was a great learning experience, and worth the time and effort we had put in.
A new low voltage digital-to-analog conversion (DAC) architecture was proposed using weighted summation of voltages at the input terminals of a floating gate MOSFET (FGMOS). An 8-bit D/A converter had been designed based on this architecture using 0.13 um CMOS technology. The circuit operated at +/-1.0V, possessed good accuracy, fast dynamic performance and low power consumption.
Guide: Dr. S.S. Rajput, National Physical Laboratory, New Delhi (now Professor at IIITM, Gwalior)
A two-stage low voltage operational amplifier for operation at +/-0.4V was designed. The amplifier incorporates a low voltage current mirror designed using standard Floating Gate MOSFETs. The operation of the proposed current mirror and op amp had been confirmed by PSPICE simulations, using 0.13 um CMOS technology.
Guide: Dr. S.S. Rajput, National Physical Laboratory, New Delhi (now Professor at IIITM, Gwalior)
The project was aimed at designing high-performance current mirrors using a fixed number of BJTs using genetic algorithms. In the end, we had implemented the algorithm successfully on MATLAB and generated some results which were verified in PSPICE, but a hard drive crash wiped out most of our work and time constraints made sure we could not pursue it again.
A project that I could not complete but very close to my heart was "Radio observation of Meteor Showers". I plan to pursue it again some time in future. I also did a project on Waveform Generator using 8085 Microprocessor and some small projects on adaptive filters using MATLAB.
1. Rohan Sehgal and S. Rajput, "A Low Voltage 8-bit D/A Converter using Floating Gate MOSFETs", Analog Integrated Circuits and Signal Processing, SpringerLink, Volume 56, Number 3, September 2008 pdf
2. Rohan Sehgal, S. Rajput and S.S. Jamuar, "A 0.8V Operational Amplifier using Floating Gate MOS technology", Proc. IEEE International Conference on Semiconductor Electronics, 2006, (ICSE 2006) Kuala Lumpur, Malaysia
3. Rohan Sehgal and Nihit Bajaji, "Matched FET Cascode Pair : Design of Non-Linear Circuits without using DC Biasing" pdf
4. Rohan Sehgal, Amandeep Singh and Wouter A. Serdijn, "CMOS Ultra Low-Power Wavelet Filter based Sense Amplifier for Cardiac Signal Analysis", PRORISC 2008, Veldhoven, the Netherlands pdf
Rohan Sehgal
rohan_sehgal (at) yahoo.com